Additionally, they sweep out holes during the erase period, helping to maintain the stored holes during the hold operation. The control gates located below the channel regions are used to operate the tunneling phenomenon during program operation. The main gates are used to control the conventional MOSFET operation during the read period and the tunneling operation during the program period. It has been proven to have excellent reliability to the effects of GBs.įigure 1 shows the cross-sectional view of the 3-D stacked ADG poly-Si-MOSFET-based 1T-DRAM cell with an ADG structure to implement high-reliability GB-independent electrical characteristics and memory performances. The proposed 3-D stacked ADG 1T-DRAM cells’ transfer characteristics, as well as memory performances, are analyzed and compared with the single-layer ADG 1T-DRAM. A TCAD simulation is used to demonstrate the superior reliability of 3-D stacked ADG 1T-DRAM to the effects of the GBs 11. In this work, the 3-D stacked ADG poly-Si MOSFET based 1T-DRAM with various average grain sizes ( G sizes) cells are investigated. However, a statistical study on the effect of the GBs in 3-D stacked ADG 1T-DRAM based on MOSFET with poly-Si has not been reported yet. An analysis of the effect of GBs in a single channel was carried out in reference 5. The GBs are important in transistors made of poly-Si because they directly affect the transistor’s electrical performances. Because they randomly varied depending on the laser irradiation energy density 10. ELC can solve the thermal budget issues, however, it cannot solve the random distribution of the GBs.
![transistor cross references transistor cross references](http://www.electronicrepairguide.com/images/transistor%20cross%20reference.jpg)
The key fabrication steps for the proposed 3-D stacked 1T-DRAM are summarized in more detail in the Supplementary Information. Fabrication steps are outlined in references 4,10 and 11. These difficulties in the fabrication can be overcome by using excimer laser crystallization (ELC) and it can implement the 3-D stacked 1T-DRAM. The second layer and beyond of the device require high-temperature processing, which can threaten existing metallization materials or cause dopant diffusion in the lower layers of the device 9. The thermal budget was one of the significant challenges in implementing 3-D stacked transistors. Based on their superior advantages in terms of the integrated fabrication technology, the poly-Si-based transistors have been widely used in 3-D memory technology in the past 6, 7, 8. In addition, the 3-D stacked 1T-DRAM is made of polycrystalline silicon (poly-Si), so high-density 3-D memory arrays can be feasible. Various groups have conducted many studies, and the ADG structure can be a great solution to overcome the RT of 1T-DRAMs 5. The stronger electric fields accelerate the recombination/generation process of the excess holes, resulting in shorter RTs in scaling of the 1T-DRAM. However, the smaller sizes of these devices tend to limit their retention characteristics due to the stronger electric field between the body and the source/drain junction. The 1T-DRAM has the advantages of being easy to manufacture and having excellent logic device compatibility 1, 2, 3, 4, 5. The 1T-DRAM operates without the use of external capacitors, instead of relying on the floating body effect. Recently, due to the complexity of the conventional DRAM’s capacitor fabrication, the 1T-DRAM has attracted great attention as a replacement for the conventional DRAM. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively.
![transistor cross references transistor cross references](https://www.moyerelectronics.com/images/categories/nte/qcross14.jpg)
The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The relative standard deviation (RSD) of the threshold voltages ( Vth) is depending on the location and the number of GBs. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays.
![transistor cross references transistor cross references](https://img.dokumen.tips/img/1200x630/reader016/image/20180804/55cf9e08550346d033b0617f.png)
![transistor cross references transistor cross references](https://alltransistors.com/pdfdatasheet_kec/image/kta1271_0001.jpg)
In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation.